The main computing blocks, which are physically implemented on FPGA, are shown inside a grey box and consist of (i) bitstream generator, (ii) [theta] (delay) computing block, and (iii) MFCV estimation.
This block reduces the data flow towards the subsequent blocks, preserving useful information for the MFCV computing .
A reference literature study , in the MFCV evaluation field, highlights that the most critical point, in the MFCV estimation, is the optimal positioning of the surface EMG electrodes along the same muscle fibre .
Both the gastrocnemii are then considered in this context for the MFCV evaluation.
The MFCV is then derived from this estimation according to (1).
According to (1), the MFCV is derived from the ratio between the interelectrode distance [DELTA]d and [theta].
This section is dedicated to the implementation and testing of the proposed FPGA-based MFCV extractor in the contexts of walking assessment.
The overall MFCV estimation system uses 7214.5 logic elements out of 32,070 available (22.5%), 136,638/4065280 memory elements RAM (3.36%), and the 6296/64140 registers (9.81%).
From the actual contraction to the MFCV generation, the overall processing stage takes about 363.5 [+ or -] 0.25 ms, of which 301 ms for the useful signal acquisition and 62.5 [+ or -] 0.25 ms for the effective computing, matching the time requirements for real-time applications.
Considering 1 s of operation, the bitstream generator operates for the 100% of the time, the IBPN evaluation block for the 34.5% of the time, the 6 estimation block, and MFCV computing, together it operates for <0.001% of the considered time.
In this paper, we presented the FPGA (Altera Cyclone V) implementation and validation of a real-time MFCV estimator, usable in cyclic dynamic contractions such as an ordinary gait.
Finally, Table 4 compares the most important and recent MFCV extraction solutions in terms of the used computing dedicated platform, the applicability in the ordinary life, number of electrodes, easiness of installation, usage, and computing performance.