The hole presented in this figure has a depth of few hundred nanometers and punches through the cap layer, the window layer, the emitter, the pn-junction, and the base of the top subcell of a MJSC presented in Figure 1.
In order to understand how the intrinsic stress of the dielectric mask influences the formation of small holes in the III-V layers, a study of the bowing of MJSC wafers was done.
As a result, the residual stress in the MJSC wafer is minimized and such stress-compensating layer can act as a dielectric mask for the etching.
Patterned test MJSC wafers did not show any etchant diffusion-related holes or other damage, confirming that this method can be used to wet-etch mesa-isolation trenches into the active III-V layers.
Implementation of the Developed Isolation Process into Microfabrication of MJSC
The proposed wet-etch isolation process for III-V/Ge solar cell structures can easily be implemented in the MJSC microfabrication.
Supplementary etching by hydrogen peroxide into the Ge emitter (typically less than 1 [micro]m) was necessary to isolate the Ge bottom cell and complete the isolation of the entire MJSC (Figure 6(d)).