Devices were fabricated by utilizing 2.9 nm HfSiO layer as high-k dielectric material in standard MOSCAP structure.
A negative slope directly revealing a negative Temperature Coefficient of Resistance (TCR) and high resistivity values of this ultrathin TiN layer in this MOSCAP structure is linked with the metal-semimetal transition phenomena observed in TiN Atomic Layer Deposition experiments .
The process, however, in totality exhibits appreciable effective mobility and permittivity of the MOSCAP structure even at low vertical fields (inversion charge density) or high values of annealing temperatures (such as >600[degrees]C), respectively, proposing the presence of an energy efficient device design with a critically thin TiN metal gate.
The work presented here deals with the formation of ultrathin TiN metal gate in combination with HfSiO dielectric, integrated into a Si MOSCAP structure, where Atomic Layer Deposition technique was fully utilized to process the device structure.
Wang et al., "The effects of process condition of top-TiN and TaN thickness on the effective work function of MOSCAP with high-k/metal gate stacks," Journal of Semiconductors, vol.