NMOSFET

AcronymDefinition
NMOSFETNegative - Metal-Oxide Semiconductor Field-Effect Transistor (electronics)
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References in periodicals archive ?
Nagase, "Low-temperature drain current characteristics in sub-10-nm-thick SOI nMOSFET s on SIMOX (separation by IMplanted OXygen) substrates," Japanese Journal of Applied Physics, Part 1: Regular Papers & Short Notes & Review Papers, vol.
Again using a BSS83 nMOSFET, a current-voltage curve was measured and the effective drain to source resistance was extracted (Fig.
The [C.sub.dsp]([C.sub.dsn]) and [C.sub.gsp] ([C.sub.gsn]) are respectively the drain-source capacitance and gate-source capacitance of the pMOSFET (nMOSFET).
The drain voltage swing is respectively limited by the ground and supply voltage levels through the nMOSFET and pMOSFET, however the gate voltage can swing above the supply voltage and below the ground level.
In the QVCO, the pMOSFETs and nMOSFETs in the signal path exhibit cyclostationary noise behavior, requiring the use of periodically varying noise statistics in analysis because the ac bias conditions are periodic functions of time.
When calculating the effective aspect ratios, it was assumed that the DGA nMOSFET and standard n-MOSFET have the same electrical parameters for the [[mu].sub.n] [C.sub.ox] and channel length modulation parameter [lambda].
Figure 5 presents the current density of the DGA nMOSFETs at the channel surface when the gate, source, drain, and body voltages were 3.3 V, 0 V, 0.05 V, and 0 V, respectively.
In this work, the gated-diode method is used to identify the interface-trapped charge density ([N.sub.it]), the surface recombination velocity ([s.sub.o]), and the minority carrier lifetime ([[tau].sub.FIJ]) in the field-induced depletion region for the nMOSFET devices using Hf[O.sub.2] gate dielectrics annealed at 500[degrees]C.
Obviously, the reverse diode current of nMOSFETs for Hf[O.sub.2] annealed at 500[degrees]C in [N.sub.2]/[O.sub.2] is smaller than that annealed in [N.sub.2].
The two shorting NMOSFETS were 1200 [micro]m x 0.4 [micro]m devices, with each laid out in a compact multifinger array of eighty 15 [micro]m x 0.4 [micro]m devices.
Lin et al., "Investigation of metallized source/drain extension for high-performance strained NMOSFETs," IEEE Transactions on Electron Devices, vol.
Hung, "Investigation of interface characteristics in strained-Si nMOSFETs," Solid-State Electronics, vol.