NMPRANational Miniature Pylon Racing Association
NMPRANational Med-Peds Residents' Association
Copyright 1988-2018 AcronymFinder.com, All rights reserved.
References in periodicals archive ?
2), it is noted that the replication of the pipeline registers of the nMPRA (nMPRA: 1-3 processor cycles; hthreats: 525-990 processor cycles; ARPA-MT: 72 processor cycles; Kuacharoen: 125 processor cycles [1]) leads to an increase in the tasks switching speed.
The interrupts prioritization scheme was extended to the events thus becoming a generalized solution for any new type of the event that can be attached to the nMPRA, to handle the situation when the multiple events are active [9].
The prioritization scheme and the MPRA architecture for 4 and 8 tasks were implemented and analyzed on Cyclone V, including: the adaptation and the implementation in Verilog code of the basic elements of the CPU (control unit, data memory and instruction memory, hazard detection unit, forward units, ALU, multiplexers); the Verilog code for the structures with the multiplied and multiplexed specific nMPRA resources: the PC register, the pipeline registers, the Register File and any other memory element.
Although nMPRA is the architecture with the multiplexing resources, the memory requirements to implement the processor varies between 10 and 35 kB, depending on the number of tasks and depth of nesting call functions, reasonable considering that in the current microcontrollers the RAM capacity for general use can vary between 256KB and 2,6MB only.
The nMPRA architecture does not have a specialized hardware interrupt controller; instead it allows the attachment of hardware interrupts and of events to the tasks in the system (an interrupt or event can be attached to a single task).
The noticeable fact about the nMPRA architecture, shown in Fig.
The interrupts in nMPRA are treated as events attached to the real-time executive or to tasks thus borrowing the priority of the tasks they are attached to.
The nMPRA architecture has some disadvantages, such as the fact that the nested level of the interrupts is limited to the number of tasks and that there is no interrupt handler vector.
The advantage of the interrupts handling system implemented by the nMPRA is that it is not necessary to use a dedicated controller for task selection and interrupts management [12].
The innovation elements introduced by this paper are the special results obtained from the synthesis, implementation and testing of the nMPRA processor, by using the FPGA Virtex-7 development kit from Xilinx.
The architecture of the nMPRA processor is based on a five stages assembly line, enabling the simultaneous execution of up to five instructions on different stages [17].