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For example, if we are using 100 nsec. DRAM, and we wish a lookup speed of around 300 nsec., we would set k = 3.
So for a k level trie, the worst-case time is (6k + 4)*clk + k*[M.sub.D], where clk is the clock cycle time (3.33 nsec. for the 300MHz Pentium), and [M.sub.D] is the memory access delay.
However, at a large clock rate (e.g., 300MHz) the difference between 12 clock cycles and 6 clock cycles (20 nsec.) is not as significant as the memory access times (75 nsec.).
The access delay from the L2 cache is 15 nsec. The delay for an access to the main memory is 60 nsec.
If the data structure is small enough to be fit in the L2 cache of 512KB, then the memory access delay [M.sub.D] is taken to be 15 nsec.; if not, it is taken to be 75 nsec.
We see that the minimum search time of 196 nsec. is attained for the leaf-pushed Variable Stride trie with four levels.
Here we see that the minimum time is 148 nsec.; however this does not meet the worst-case deletion time requirements.
Time for Dynamic Memory (KB) Time to Find Memory (KB) Program Using Levels Database Hash (sec.) (16, 24, 32) (msec.) from dynprog MaeEast 750 4250 650 3250 MaeWest 150 2250 287 1250 Pac 8 512 55 512 Paix 0.1 256 15 256 Random Database Search (nsec.) MaeEast 190 MaeWest 190 Pac 180 Paix 180 When compared to the worst-case figure for 5 levels for the unexpanded form of MaeEast, we have roughly twice the memory requirement (3220KB versus 1600) but a factor of 1.66 reduction in the worst-case number of memory accesses (3 versus 5).
We assume a cheap forwarding engine (say US $50 assuming high volumes) operating at a clock rate of 2-10 nsec. We assume the chip can place its data structure in SRAM (with say 10 nsec.
For example, consider an IP lookup chip that can do wire speed forwarding at OC-48 rates (one lookup every 166 nsec.), can handle 50,000 arbitrary prefixes, and can do an update every msec.
However, since even our fastest trie schemes take 3-4 memory accesses, implementations (e.g., routers that support OC-48 links) that require lookup times faster than say 300 nsec. will require pipelining.
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