PMOSFET

AcronymDefinition
PMOSFETP-Type Mosfet
PMOSFETPositive - Metal-Oxide Semiconductor Field-Effect Transistor (electronics)
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References in periodicals archive ?
Ohuchi et al., "A high performance pMOSFET with two-step recessed SiGe-S/D structure for 32nm node and beyond,' in Proceeding of the 36th European Solid-State Device Research Conference (ESSDERC '06), pp.
How the variation in thickness of the Hf[O.sub.2] metal gate stack PMOSFETs affects the kinetics of E' centers and generation of interface traps has not been thoroughly investigated.
This study is conducted for PMOSFETs with varied thicknesses of dielectric layers.
The phase shift across a set of components ([C.sub.L], [C.sub.R], [C.sub.gsp], [L.sub.R]) is 90[degrees] so that the phase shift of the coupling varactor-inductor loop is 360[degrees] and the waveforms of gate voltages (and drain voltages) of pMOSFETs are quadrature.
In the QVCO, the pMOSFETs and nMOSFETs in the signal path exhibit cyclostationary noise behavior, requiring the use of periodically varying noise statistics in analysis because the ac bias conditions are periodic functions of time.
VCO output amplitude variations due to the low-frequency noise injection can also modulate the phase delay associated with the nMOSFETs and pMOSFETs. The signal swing of the QVCO causes the operating point of the MOSFETs to vary periodically and the MOSFETs exhibit an AM-PM transfer function that is dependent on its operating characteristics.
As shown in Figure 4, the electric potential of the terminals in the pMOSFET can be expressed as (2), where [V.sub.solar], [V.sub.batt], and [V.sub.sc] denote the voltage of solar energy harvester, lithium polymer battery, and super capacitor, respectively.
Conversely, the pMOSFET is switched on when the solar energy source is insufficient ([V.sub.gs] < [V.sub.th]), and then the discharge circuit of the lithium polymer battery is connected.
So the Schottky diodes D1, D2, and D3 conduct, and the pMOSFET turns off.
Apart from the S/D engineering, a28-nm HK first/meta gate last technology was used to prepare the pMOSFET samples for this work.
In this paper, we have investigated the effect of compressive strain on low-frequency noise in HK pMOSFET. Through RTN measurement, we found that the HK pMOSFET with the embedded SiGe S/D has a shorter distance of the oxide trap position from the insulator/semiconductor interface.
Hsieh et al., "Investigation and localization of the SiGe source/drain (S/D) strain-induced defects in PMOSFET with 45-nm CMOS technology," IEEE Electron Device Letters, vol.