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For this example, where the power/ground plane is closer to the bottom of the board than the top, the loop area would be smaller and the connection inductance would be lower if the capacitor was mounted on the back side of the board rather than the top side.
The lack of IO interconnect models made the simulated power/ground noise at driver and receiver sides unpredictable, especially when a large number of drivers switch simultaneously.
The concurrent simulation method provides the highest degree of accuracy, especially as the number of shared power/ground networks increases.
It addresses the challenges associated with global couplings of power/ground noise, substrate noise, and package/PCB capacitive and inductive noise for memory components (Flash and DRAM), high-speed I/Os (HDMI and DDR), and analog circuits such as power management ICs.
Current flows in the signal net from driver to receiver; and so-called "return" current flows in the power/ground planes back to the driver to complete the required loop.
It efficiently simulates large-scale macros including the impact of clamp's snap-back characteristics, power/ground and substrate networks, and package parasitic, with convergence property.
Leary fully describes the use of capacitive power/ground planes in a circuit board and uses the same calculation for the amount of capacitance developed as all the other planar capacitors in this field.
It contains spatial and temporal switching current profile, as well as parasitics of non-linear on-chip devices including decaps, loading capacitance, and power/ground coupling capacitance.