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8 represents [P.sub.crt,rnd], for the proposed QMEC scheme.
Area, power consumption and delay of Codec, residual flit error rate, interlink power and link-swing voltage and reliability are the prime factors that account for the performance of the proposed QMEC compared to other codes considered for the experimental purpose are discussed in this chapter.
The performance of the proposed QMEC codec along with other error correcting codes is evaluated by implementing the schemes in Vivado 15.1 for the Zynq7000 series xc7z020clg484-1chip.
As depicted in the above Table I, it is evident that each codec has error correcting capability ranging from single to a maximum of five bits in the earlier researches; however, our proposed technique, QMEC has error correcting capability of nine bits.
The proposed QMEC codec corrects nonuple errors with cross talk avoidance by the process of quintuplication.
Also, the delay of the proposed QMEC is less than QMEC without Manchester.
Though we ran eight different scenarios, considered only DAP, CADEC, JTEC, MBRBEC and proposed QMEC for computing the results.
QMEC code registered a low residual rate in correcting the combination of errors and proved that the proposed code is capable of correcting errors extending to nonuple.
The proposed QMEC code achieves 71% reduction in voltage consumption the d flit error rate of 10-20 than MBRBEC and corrects nonuple errors in contrast to five by MBRBEC.
In our earlier results, it has been mentioned that the proposed QMEC has high reliability while consumes less voltage which is proportional to link power consumption with link length of 1mm.
In this paper, the performance of the proposed QMEC code has been studied and compared with DAP, Ex-Hamming Code, CADEC, JTEC, MBRBEC.
The proposed QMEC though utilizes more LUTs but consumes 16% less power when compared to MBRBEC.
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