RECONFIG

AcronymDefinition
RECONFIGReconfiguable Computing and FPGAs (conference)
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References in periodicals archive ?
[132] Poona Bahrebar and Dirk Stroobandt, "Adaptive and reconfigurable fault-tolerant routing method for 2D networks-on-chip," in International Conference on ReConFigurable Computing and FPGAs (ReConFig'14), 2014, pp.
Figure 10: Services of the Reconfig. Effector aspect ReconfigurationEffector Aspect ...
Resources Available Static Slice registers 663360 18413 Slice LUTs 331680 16209 LUT-FF Pairs 331680 7026 BRAM 1080 47 DSPs 2760 0 Bitmap size Clearing time -- -- Reconfig. time Resources RP 0 RP 1 Slice registers 93600 (51.42%) 102400 (46.97%) Slice LUTs 46800 (78.81%) 51200 (72.05%) LUT-FF Pairs 46800 (50.97%) 51200 (47.39%) BRAM 170 (28.24%) 170 (28.24%) DSPs 460 (24.35%) 460 (24.35%) Bitmap size 4,762 MB 4,762 MB Clearing time 0.0826 [+ or -] 0.0047 s 0.0836 [+ or -] 0.0044 s Reconfig.
Fahmy, "Generalised parallel bilinear interpolation architecture for vision systems," in Proceedings of the International Conference on Reconfigurable Computing and FPGAs (ReConFig '08), pp.
Owall, "Design of coarse-grained dynamically reconfigurable architecture for DSP applications," in Proceedings of the 2009 International Conference on ReConFigurable Computing and FPGAs, (ReConFig '09), pp.
Deschamps, "FPGA implementations of BCD multipliers," in Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig '09), pp.
Stamatakis, "A versatile udp/ip based pc-fpga communication platform," in Proceedings of the International Conference on Reconfigurable Computing and FPGAs (ReConFig '12), pp.
Ordaz-Moreno, "VHDL core for 1024-point radix-4 FFT computation," in Proceedings of the proceedings of the IEEE International Conference on Reconfigurable Computing and FPGAs (RECONFIG '05), pp.
Sima, "Fixed-point CORDIC-based QR decomposition by givens rotations on FPGA," in Proceedings of the International Conference on Reconfigurable Computing and FPGAs (ReConFig '11), pp.
Packet Overhead loss rate Reliability Reconfig. Unreliable 31% -- -- Reliable 0% 128% -- Autonomous 0% 60% 40% TABLE 2: Measured packet loss for all combinations of mapping algorithms and network traffic mixes.
Danger, "Efficient dual-rail implementations in FPGA using block RAMs," in Proceedings of the International Conference on Reconfigurable Computing and FPGAs (ReConFig '11), pp.
Ferreira, "From instruction traces to specialized reconfigurable arrays," in Proceedings of the International Conference on ReCon-Figurable Computing and FPGAs (ReConFig '11), pp.