It has a robust set of features including Auto RTS/CTS Hardware Flow Control, Auto XON/XOFF Software Flow Control, TX/RX FIFO Counters, selectable or programmable transmit and receive FIFO
trigger levels, and Fractional and Independent TX/RX Baud Rate Generators.
Each channel has a 128 byte transmit and receive FIFO
to increase the service interval and reduce the overall UART interrupt servicing time.
Each serial port is equipped with large 64-byte transmit and receive FIFO
buffers that minimize CPU interaction lot more efficient data processing.
The receive FIFO
can contain up to 128 bytes of data, accessible through the SPI; cyclic redundancy check (CRC) of the received data is performed automatically.
Back-to-back transmission with minimal interface latency is facilitated with 3 Kbytes of transmit and 3 Kbytes of receive FIFO
for each port.
Media Access Controller (MAC) with 512 bytes transmit first-in/first-out and 512 bytes receive FIFO
Optional type 16850 UARTS with 128 bytes of transmit and receive FIFO
may be specified for reducing processor overhead.