RTL

(redirected from Register transfer level)
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AcronymDefinition
RTLRegister Transfer Level (VHDL)
RTLRegister Transfer Level
RTLRetail (hardware or software release in its final version, as opposed to beta)
RTLRight to Left
RTLReady to Launch (various companies)
RTLRight To Life (political party, NY)
RTLRun Time Library
RTLResponding to Life
RTLrectal
RTLRantoul (Amtrak station code; Rantoul, IL)
RTLReady To Learn (PBS)
RTLRide The Lightning (Metallica)
RTLReal Time Linux
RTLRound Trip Latency
RTLRaster Transfer Language
RTLReal Time Localization
RTLRealtek Lan
RTLReliance Telecom Ltd (India)
RTLRedwood Toxicology Laboratory (drug testing facility; Santa Rosa, CA)
RTLRegister Transfer Language
RTLResistor Transistor Logic
RTLRe-education Through Labour (China)
RTLRéseau de Transport de Longueuil
RTLRegional Team Leader
RTLRadio Télévision Luxembourg (Luxembourg Television and Radio)
RTLRadio Timor Leste (East Timor)
RTLReal Time Logic
RTLRegister Transfer Logic (semiconductors)
RTLRuntime Language
RTLReconstituted Tobacco Leaf (blend construction)
RTLReady to Load
RTLResolution Team Leader
RTLReduced Tillage Linkages
RTLRide the Lobster (unicycling race)
RTLRated Tensile Load (suspension insulators)
RTLRegister Transfer List
RTLRestricted Target List
RTLRadial Transmission Line
RTLRoutine Test Load (suspension insulators)
RTLRadio Telex Letter
RTLRadiating Transmission Line
RTLRegimental Training Line
RTLResearch & Technology Laboratories (AVRADCOM)
RTLRolling Target List
RTLRefrigerated Transmission Line
RTLRadio Team Leader
RTLReinforced Tile Lintel
RTLResponsible Task Leader
RTLRegeneration Thermo-Luminescence
RTLRate Tracking Loop
RTLRecovery Technical Limit
RTLResource Tie Line
RTLRadiative Transfer Laboratory (University of Kentucky; Lexington, KY)
References in periodicals archive ?
Typically, those designing SAS silicon will make or buy the simulation code they need to verify the RTL (Register Transfer Level) code, ensuring that the different scenarios have been verified.
"Using this approach, STMicroelectronics has been able to verify embedded software six months prior to register transfer level (RTL) completion, significantly reducing their time-to-market."
It also propagates faults through the Verilog-XL simulator at the register transfer level (RTL) of a design.
Driven by a growing demand for low-power solutions, IEEE 1801-2015 provides a more structured approach to abstraction, with inherent IP-based power modeling and an API to a formalized information model, helping to bridge the gap between the detailed world of Register Transfer Level (RTL) and Unified Power Format (UPF) implementation and the abstract world of system level IP power modeling, analysis and optimization.
Design teams in Japan began using the Certitude system to evaluate the quality of their current register transfer level (RTL) simulation-based verification environments, to improve internal IP quality and to qualify third-party IP designs for "FR" product families, the company's 32bit RISC microcontroller for automotive applications.
(Santa Clara, Calif.), an EDA company that offers formal register transfer level (RTL) functional verification products, has joined the Cadence Design Systems, Inc.
Mentor Graphics Corp., today announced availability of a new solution for X-value verification in register transfer level (RTL) and gate level designs.
The register transfer level (RTL) to GDSII reference design flow shortens time-to-market for ARM core-based designs.
Cross-debugging between signal processing and register transfer level (RTL) models and simulation link of digital/RF capabilities result in significant time and cost savings.
Calypto Design Systems, Inc., the leader in Electronic System Level (ESL) hardware design and Register Transfer Level (RTL) power reduction, today announced that Core Logic Inc., Korea s leading fabless semiconductor manufacturer, has adopted PowerProA CG as their primary power optimization tool for designing their complex system-on-chip (SoC) products.
It compares register transfer level (RTL) code to flattened or hierarchical netlists for multi-million gate designs in minutes or hours, instead of days or weeks required by comparable tools.