SMROM

AcronymDefinition
SMROMSynchronous Mask Read Only Memory
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Major organization : SMROM FONT-ROMEU GAT TARGASONNE
2 watts (maximum) -- Operating frequency: 133MHz -- On-chip cache: Instruction cache: 8KB (2-way) Data cache: 4KB (2-way) Burst refill and locking functions -- Memory Controller: SRAM: Supports 8 channels of SDRAM, Flash (DIMM), SGRAM or SMROM memory ROM: Supports 8 channels of ROM, page mode ROM, MROM, EPROM, EEPROM SRAM, Flash, and I/O devices -- Timer/Counter: 3-channel 24-bit up-counter, interval and watchdog, 3 external (multiplexed) timer output pins, external input clock -- Interrupt Controller -- PCI Controller: 32-bit, 33 MHz.