SSRAM

AcronymDefinition
SSRAMSynchronous Static Random Access Memory
References in periodicals archive ?
The device provides OC-48 performance that seamlessly interfaces to ASICs and network processors through the industry standard SSRAM interface.
PMC-Sierra Ships ClassiPI Packet Classification Processor
port 1200 uses an advanced programmable classification engine to non-intrusively monitor packet data on an SSRAM interface or the high-speed IX data bus on the Intel(R) IXP1200 network processor.
Solidum and IDT Introduce Complete Classification Evaluation System
The CYNCP80192 offers an SSRAM interface, offloads table and pipeline management from the processor, and offers a silicon-optimized ASSP solution to customers.
Cypress Launches Industry's Fastest Low-Power Network Search Engine
Additionally, the iAP uses a ZBT/DCD SSRAM interface, making it simple to incorporate the iAP into a wide variety of NPU or ASIC-based designs, including those based on the complete iFlow Data Path Processing Platform (DP3) chipset.
Silicon Access Networks Delivers World's Highest Integration Solution for Network Address Lookup
The LNI8010 provides an SSRAM interface on the system bus that enables easy interfacing to popular network processors as well as to system ASICs.
Lara Networks, Inc. Introduces Industry's First Ever Network Database Co-Processor to Enhance Interoperability Between Network Processors and Lara's Search Engines
The controller provides a 64-bit wide port that operates at a full 125Mhz data rate, and supports SSRAM, SDRAM, and Flash EEPROM with up to a 1GByte-per-second transfer rate.
Chameleon Systems Introduces the Industry's First Reconfigurable Communications Processor Family
port 1100 examines packet data on an SSRAM interface or equivalent, as it is written into a memory or FIFO queue.
Solidum Introduces PAX.port 1100 Classification IC for Multi-Gigabit Network Processing: New Classification IC to Dramatically Boost Application Performance
The controller supports DDRAM, SDRAM, DRAM, Flash, SSRAM and ROM devices, as well as multiple backside host interfaces and memory banks.
Altera and Palmchip Partner to Speed Time-to-Market For System-On-A-Programmable-Chip Integration
600 MHz Alpha 264 CPU and 2MB SSRAM cache in Alpha Slot B module
API Announces Program to Encourage ISVs And IHVs To Develop Alpha Linux Solutions; Offers Immediate Saving On Alpha Workstations With Bundled GNUPro Toolkit from Red Hat
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