Table 3 presents the rated current required to switch the state of MLC STT-RAM for each transition .
However, these spilling policies assume uniform write distribution and hence will fail to choose the most energy-efficient node from the potential spilling list if MLC STT-RAM is employed as register.
In this work, since we consider registers built by MLC STT-RAM where writes with different state-transitions cost different energy, the conventional approach is not appropriate any more.
Motivated by this consideration, a spilling policy guided by state-transition cost analysis is proposed so as to reduce energy consumption in MLC STT-RAM.
This section first describes the framework overview of the proposed approach and then presents the spilling cost model driven by state transition of MLC STT-RaM. Finally, the algorithm for SSCM-based register allocation is presented.
In this paper, we propose a cost-based method to choose spilling variables when MLC STT-RAM is employed as the register.
In this subsection, a spilling cost model is presented to illustrate the spilling priority, determined based on state-transition profiling information of MLC STT-RAM.
Considering a MLC STT-RAM with 2 bits per cell, the state S contains [2.sup.2] = 4 states.
We calculate the write energy of every energy in MLC STT-RAM at 45 nm technology node based on data reported in [18,20] and assume that 10 ns pulse duration is applied.
In this way, the allocator can make a better decision on register assignment based on the exact STT-RAM register state-transition usage information.
By keeping the node (variable) with less transition energy in register instead of memory, it helps avoid expensive spills when considering the state-transition costs of MLC STT-RAM.
The architectural parameters of the MLC STT-RAM registers are listed in Table 5 .