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The absolute delay measurements obtained through simulation are 162 ps for TGFF and 196 ps for m[C.sup.2]MOSff1 which is in close agreement with the theoretical values 160.55 ps and 166.27 ps, respectively (typically within 15% error).
Apart from the clock load, the capacitance value at internal nodes of m[C.sup.2]MOSff1 is reduced as compared to TGFF by eliminating transistors TN6 and TP6 from the feedback structure.
It can be easily concluded from calculations above that a total of 19.34 fF capacitance has been reduced from the internal nodes in the critical path of m[C.sup.2]MOSff1 in comparison to TGFF. This leads to reduced internal power dissipation at these nodes as lesser capacitance has to be charged or discharged per clock cycle.
Since only sixteen transistors are used for circuit realization of m[C.sup.2]MOSff1, power dissipation is comparable to TGFF. It is worth noting that GMSL and DTLA offer minimum clock load, as a result, these topologies exhibit least power dissipation at lower switching activities.
The layouts for TGFF and m[C.sup.2]MOSff1 are shown in Figures 17 and 18, respectively.
Again, it can be clearly observed that there is only a slight difference in the power dissipation of TGFF and m[C.sup.2]MOSff1 at different switching activities.
It was noticed that the power consumption of the m[C.sup.2]MOSff1 based counter is comparable to the TGFF at varying frequencies.
However, it is to be pointed out that m[C.sup.2]MOSff1 in a manner similar to TGFF starts to fail at SS corner for lower values of [] [34].
Using the new feedback approach, a modified topology m[C.sup.2]MOSff1 is proposed with decreased parasitic capacitances at internal nodes in comparison to the TGFF which is the finest design in terms of PDP.
The T flip-flop designed using TGFF is shown in Figure 24.