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ULSIUltra Large Scale Integration
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The substrates intended for ULSI circuitry are patterned with holes, trenches, and other features with diameters that are currently around 130 nm, soon to be reduced below 100 nm, and even 70 nm.
13 Electrochemical Deposition Process for ULSI Interconnection Devices (Tetsuya Osaka and Masahiro Yoshino).
Brion's uniquely fast computational lithography technology consistently gives optimum results across the areas of process development, mask design and litho manufacturing," said Tatsuhiko Higashiki, Senior Manager of Toshiba's Process & Manufacturing Engineering Center, Advanced ULSI Process Engineering Dept.
Flash Annealing for ULSI and Beyond Si Short Time Thermal Processing: From Electronics via Photonics to Pipe Organs
As a user of Brion's computational lithography and NuFlare's reticle writing and inspection systems, we are pleased to support this collaborative effort," said Tatsuhiko Higashiki, senior manager, Advanced ULSI Process Engineering Dept.
Furthermore this technology facilitates 10 times more accurate and much faster testing of time margins in integrated circuits, wherein such advantages are critical for effective testing of ULSI chips comprising mixed-mode signal processing.
Stork was Director of the ULSI Research Lab and later the Internet Systems and Storage Lab at HP Laboratories, Hewlett-Packard.
They include evaluation boards such as Hitachi ULSI Systems' Solution Engine, and the Renesas E10A-USB emulator.