Table 4 indicates the comparison between the existing VLSI implementation of VBSME and proposed implementation.
From comparison among FPGA implementation of VBSME architectures also we can observe that number of LUTs used by proposed design is higher but at same time design offers higher frame processing rate.
As per (2) and (3) hardware and power efficiency are computed for existing and proposed VBSME implementation and shown in Table 6.
Implementation results show that proposed VBSME architecture outperforms in area utilization compared to existing 1-pixel scan, 4-pixel scan, and 16-pixel scan architectures due to 16-pixel z scanning pattern.
Hao, "A high-performance reconfigurable VLSI architecture for VBSME in H.264," IEEE Transactions on Consumer Electronics, vol.
Ienne, "Scalable and low cost design approach for variable block size motion estimation (VBSME)," in Proceedings of the International Symposium on VLSI Design, Automation and Test (VLSI-DAT '09), pp.
Caption: Figure 5: Proposed hardware implementation of VBSME.