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The WDDL netlist is first partitioned into 2 parts: a partition that contains true gates and a partition that contains dual gates.
Table 3 summarizes the placement statistics obtained for the WDDL DES and QUIP netlists.
In the adjacent partitioning, the hypergraph of all the WDDL circuit is considered.
In fact, we can see a gain of 74% of the average [DELTA]delay in WDDL designs.
We have experimentally determined that setting the minimal f(Diff_sw_nb(i, n, j)) to 0.1 is the best value for WDDL designs mentioned in this paper.
Indeed, the delay balance is improved by 76% in WDDL DES design, and by 81% in all WDDL designs compared to results obtained with adjacent placement and shortest path PathFinder routing algorithm.
In fact, the average delay balance is improved by 69% in all WDDL designs and the Total_Diff_sw_nb is reduced by 71% compared to results obtained with adjacent placement and shortest path PathFinder routing algorithm.
Table 6 presents results of routability-driven (congestion-based) routing and timing-balance-driven routing applied to adjacent placed WDDL netlists in cluster-based mesh FPGA, where each cluster contains 2 LBs.
It is possible to have a WDDL cryptographic design which contains dual-rail signals and single-rail signals.
But, it is obvious that an architecture containing more equivalent wires is more adapted to differential pair routing of WDDL design.
All dual signals of WDDL designs are routed with the same number of switches (Sw.Mis.Signals = 0).
Figure 17 shows the distribution of the C_ratio of all the nets of WDDL DES design obtained with the unconstrained placement and routing, with adjacent placement and timing-balance-driven routing, and with adjacent placement and differential pair routing.
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