(redirected from Wafer Level Chip Scale Packaging)
WLCSPWafer Level Chip Scale Packaging
WLCSPWafer Level Chip Scale Packing (DDR RAM package)
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According to STATS ChipPAC the new 197,000 sq ft building will be located next to its current factory in Yishun, Singapore and will enable the company to expand its manufacturing capabilities for advanced wafer level technologies including embedded Wafer Level Ball Grid Array (eWLB), Wafer Level Chip Scale Packaging (WLCSP), Integrated Passive Devices (IPD) and Through Silicon Via (TSV).
of Singapore, a globally leading provider of chip packaging and test services, yesterday inaugurated a facility at its Taiwan subsidiary to deal with 300mm wafer bump and wafer level chip scale packaging (WLCSP).
Therefore, the strong demand for 65/55-nanometer and below wafer manufacturing has prompted testing and packaging companies to expand their capacity to fill orders from upstream manufacturers for wafer bumping, WLCSP (wafer level chip scale packaging) and mixed-signal integrated circuit and high-speed logic circuit testing.