(redirected from Write buffer)
Also found in: Encyclopedia, Wikipedia.
WBUFWrite Buffer
Copyright 1988-2018 AcronymFinder.com, All rights reserved.
References in periodicals archive ?
The CAT24C512 and CAT24M01 employ 256 byte and 128 byte page write buffers respectively.
(9) write miss ratio = # write buffer misses - # modified pages purged/# logical writes
A write is considered a write buffer miss if the page being written to is either not in the buffer pool or is in a clean state in the buffer pool.
Therefore, allowing the write buffer to vary in size as needed is generally a good idea for these workloads.
The latency shown for writes is the time for retiring the request from the write buffer. This latency is the time for acquiring exclusive ownership of the line, which does not necessarily include the time for receiving acknowledgment messages from invalidations, since the release consistency model is used [Gharachorloo, et al.
A processor stalls while waiting for writes to complete in two situations: (1) when executing a write instruction if the write buffer is full and (2) during a read miss if previous writes must complete before the read miss can proceed.
Features include single 3.0 V power supply, asynchronous access times up to 70 ns for the 16Mb and 9Ons for the other densities, page mode access times up to 25 ns, 16 word performance-enhancing write buffer, small 64kB sectors with erase times up to 400 microseconds, minimum of 20 years data retention at 125[degrees]C and minimum of 100,000 write/erase cycles per sector.
Other features of the new architecture include a new Instruction Fetch Unit (IFU), an Address and Data Unit (ADU), support for Dual-Port RAM, a Write Buffer and three register banks.
Once two devices on the bus have negotiated a speed, the initiator sends out a Write Buffer command to the device to test transfers at the negotiated speed.
Also, the six-entry write buffer on the 21164 is not able to retire the writes fast enough to keep up with the computation.
The summary for the slowest run (not shown) shows that the percentages of stall cycles attributed to D-cache miss, DTB miss, and write buffer overflow increase dramatically to 44.8-44.9%, 14.0-33.9%, and 0.0-18.3% respectively.