XGMII - What does XGMII stand for? The Free Dictionary
References in periodicals archive
specification for passive interconnection to 10G Ethernet devices.
The XGEMAC provides XGMII
interface to the line side and a flexible backend interface to the user logic on the system side.
The internal XGMII
control information is preserved and reconstructed on the receive side.
The PM8358 QuadPHY 10GX is a bi-directional XGMII
to 4 lanes of 1.
HCLT also used Blast Fusion to complete three low-power physical designs with complexities up to 500K gates including a datapath controller, XGMII
multiplexor, and a communications IP.
interface is a key part of Lattice's Physical Coding Sublayer (PCS) Intellectual Property core.
Emulex's demonstration features a custom designed circuit board that utilizes a Xilinx Virtex(R)-II field programmable gate array (FPGA) to create an industry standard XGMII
compliant parallel data interface.
For example, designers can build a 20 Gbits/sec bridge for 10 Gbits/sec Ethernet; the high-speed SERDES interfaces contain dual-XAUI interfaces with configurable back-end interfaces such as XGMII
implemented on the FPGA side.