XGMII10 Gbit Media Independent Interface
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3ae XGMII specification for passive interconnection to 10G Ethernet devices.
The XGEMAC provides XGMII interface to the line side and a flexible backend interface to the user logic on the system side.
HCLT also used Blast Fusion to complete three low-power physical designs with complexities up to 500K gates including a datapath controller, XGMII multiplexor, and a communications IP.
The XGMII interface is a key part of Lattice's Physical Coding Sublayer (PCS) Intellectual Property core.
Emulex's demonstration features a custom designed circuit board that utilizes a Xilinx Virtex(R)-II field programmable gate array (FPGA) to create an industry standard XGMII compliant parallel data interface.
For example, designers can build a 20 Gbits/sec bridge for 10 Gbits/sec Ethernet; the high-speed SERDES interfaces contain dual-XAUI interfaces with configurable back-end interfaces such as XGMII implemented on the FPGA side.