NetLogic Microsystems' AEL2020 device provides full Physical Coding Sublayer (PCS), PMA, and XGXS
sub-layer functionality through the consolidation of the receiver and transmitter PHY functions on a single chip along with the integration of encode/decode/alignment logic, FIFOs, on-chip clock generation and data recovery, multiple loop-back features, PRBS Ethernet frame generation and verification for both the line- and the system-side.
Customers can design scalable and expandable customized solutions by making use of LSI Logic's extensive library of CoreWare(R) IP blocks, including GigaBlaze(R) and HyperPHY(TM) high-speed SerDes, 10/100 Ethernet PHY, 10/100/Gig/10Gig MACs, XGXS
, PCI Express, PCI, PCI-X, PCI-X 2.
NetLogic Microsystems' 10GBASE-LRM compliant AEL2005 device, which is shipping to several Tier One customers, is a highly integrated PHY product with full PCS, PMA and XGXS
sub-layer functionality, and offers significant power and associated system cost savings for high-density datacenter switch designs.
The chip's XGXS
, PCS, and PMA blocks incorporate serializer/deserializer, phase-locked loop (PLL), clock data recovery (CDR), transmitter/receiver elastic FIFO(5), 8- to 10-bit encoder/decoder, 64- to 66-bit encoder/decoder, and gearbox functions.
, PCS and PMA sub layers of the 10GE standard are incorporated in both TenGiPHY transceivers.