L2C
Also found in: Encyclopedia.(redirected from level two cache)
| Acronym | Definition |
|---|
| L2C | Lead-to-Cash |
| L2C | Learn to Code (computer programming) |
| L2C | Level Two Cache |
| L2C | Learning to Collaborate (research project) |
| L2C | Load to Card |
| L2C | Layer 2 Control |
| L2C | Live2call (band) |
References in periodicals archive
LUKAS CHUCHROWSKI Most Successful Learner on Level One travel and tourism course FREYA COLEMAN, Highest Achieving Learner on B-Tec sports science programme SHAUNA DANIELS, Alison Eddy Memorial Award for Level One hairdressing SOPHIE WOODWARD,
Level Two CACHE childcare programme LAITH HASAN, distinction in the B-Tec introductory diploma in IT.
The
level two cache is shared by the two independent processors on a single chip.
The Timna processor, expected to appear in .18 micron technology at the end of next year, will include a Pentium II-class processor, graphics controller, 128Kb of
level two cache, and a Direct Rambus memory controller, says the report.
A 400MHz version with 2Mb
level two cache and I00MHz system bus is now sampling.
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